It is known that channel packing density (channel width per unit area) and cell density play important roles in the aspect of improving the Performance/Area-cost ratio of trench semiconductor power device. Therefore, many kinds of trench semiconductor power devices were disclosed in prior arts trying to achieve higher channel packing density and cell density.
In U.S. Pat. No. 6,737,704, a trench MOSFET cell with source-body contact on inner circumferential surface was disclosed, as shown in FIG. 1. This cell was formed on an N+ substrate 100 on which a lightly doped N epitaxial layer 102 was grown. A plurality of trenched gates were formed inside said epitaxial layer 102 and each filled with doped poly-silicon 104 in its lower portion over an gate oxide layer 108. Beside said trenched gates, there were P-body regions 112 inside which a plurality of n+ source regions 114 were formed in an active area and adjacent to the upper portion of said trenched gates sidewalls, and in the meanwhile, a plurality of P+ body contact regions 113 were formed surrounding said n+ source regions 114. A layer of front metal 118 was directly filled into upper portion of said trenched gates to contact said n+ source regions 114 and also contact said P-body regions 112 indirectly.
What should be noticed is that, the body contact regions 113 occupies a large amount of a mesa area locating between two adjacent trenched gates, which limits the increasing of cell density mentioned above. Besides, FIG. 2 and FIG. 3 lead to the conclusion that when the mesa width ‘a’ is smaller than the trench width a stripe cell design is better than a closed cell design due to higher channel packing density and resulted low on-resistance Rds (resistance between drain region and source region) in the stripe cell design. However, since the disclosed structure of the trench MOSFET in prior art is a closed cell design, even if the limitation of requiring large mesa area can be solved by improved technique, the lower channel packing density inherently led by the closed cell still have the problem of high on-resistance Rds.
In U.S. Pat. No. 7,402,863, another trench MOSFET cell with source-body contact on inner surface is shown in FIG. 3. Comparing to FIG. 1, in this prior art, an additional Ti/TiN layer 111 was added as barrier layer before the deposition of front metal layer 118′, however, considering the disadvantage introduced above, nothing had been improved.
Accordingly, it would be desirable to provide a new and improved trench MOSFET configuration with high cell density and high channel packing density while improving the Performance/Area-cost ratio.